Application of inkjet printing for 3D integration

Inkjet printing is an attractive deposition tool to complement the traditional processing methods used in microelectronics integration. Its maskless, digital and non-contact nature provides many generic benefits, such as savings in processing steps and material usage, production flexibility and scalability to large areas. In addition, inkjet printing can be utilized in the integration of e.g. silicon and polymer or paper based systems, such as for the new wave of hybrid large-area, flexible devices, which are out of the scope of traditional clean room processing. In this paper, we study the process of metallization of a Through-Silicon Via hole (TSV) by inkjet deposition. We describe the process of sample preparation and characterization. We finally demonstrate the creation of a fully inkjet printed 3D electrical interconnection using a Kelvin TSV test structure. Introduction Inkjet printing offers a unique approach to microelectronics 3D integration as it could provide a leap to maskless patterning and deposition to complement traditional microfabrication processes. Potential benefits are savings in processing steps and material usage, production flexibility, scalability to large areas, non-contact deposition on fragile layers or micro scale topographies and compatibility with a wide range of substrate materials for heterogeneous integration. The use of piezoelectric inkjet printing has previously been studied for over edge interconnections on chips and dies as a substitute for wire bonding [1], droplet based dispensing of micro bumps for flip chip bonding [2], and conductor dispensing for Through-Silicon Via (TSV) hole and redistribution layer metallization [3, 4, 5]. Industrial piezoelectric inkjet printing has similarly been applied for the fabrication of printed multilayer interconnections of epoxy-molded components in a system-in-package [6]. Other possible applications for inkjet printing in 3D integration include high accuracy adhesive material dispensing for attaching dies and building 3D topographies in the micrometer scale to assist in conductor patterning in subsequent processing steps. Inkjet also enables non-contact conformal patterning of insulation/passivation and encapsulation layers over 3D topography [7]. Ultimately, in combination with laser etched through-silicon via holes, inkjet printing could facilitate a fully maskless 3D integration process as it could replace three mask levels worth of cleanroom processing: deposition of conductor material into through-silicon via holes, patterning of the redistribution layer and deposition of flip chip bumps. In this paper, we demonstrate the use of inkjet printing for deposition of a metal nanoparticle ink for creating a vertical electrical interconnection through a TSV hole. Forming an electrical contact over a sharp edge formed by wet etching on silicon is also studied as a reference to the TSV metallization process. Experimental Materials and equipment Printing was performed using a PiXDRO LP50 advanced research printer from Roth & Rau driving an industrial piezoelectric multinozzle printhead with a nominal drop volume of 10 pL (SX3, Fujifilm Dimatix). The conductive ink used was a silver nanoparticle ink (DGP 40LT-15C, Advanced Nano Products) with solids loading of 30 wt-% dispersed in TGME (triethylene glycol monoethyl ether, b.p. 256 °C) as main solvent. Intermediate drying steps were performed offline using a hotplate (Linkam TMS 93) and final sintering of the printed samples was performed using a hot air oven. The printing process optimization tests for TSV metallization were performed on Deep Reactive Ion Etched (DRIE) blind TSV structures with tapered sidewalls (sidewall angle 84°) and thermally grown silicon dioxide insulator. <100> silicon wafers were used in all the tests. The TSV fabrication process is described elsewhere [8]. Forming an electrical contact over a sharp edge was tested with wet etched silicon trenches (length 400 μm, height 110 μm and sidewall angle 54°). Electrical testing of metallized Kelvin TSV test structures was done using tapered TSVs reaching through a 240μm thick substrate. In these test structures a low temperature deposited silicon dioxide was used as insulator material. Through-silicon via hole and redistribution layer metallization process Critical aspects in the TSV hole filling process were the via hole dimensions, droplet volume and printer accuracy, processing temperature and the strategy with which droplets were deposited into the hole. A large volume fraction of the nanoparticle ink is the carrier solvent which had to be removed during the filling process in order to obtain sufficient metallization thickness while preventing overfilling of the hole. Various filling strategies were applied for controlling this, mainly by varying the number of subsequent droplets and the deposition and drying delays and temperature. The effect of these strategies on the metallization quality after sintering was studied, using blind via holes with top diameter, bottom diameter, height, volume and pitch of 79 μm, 53 μm, 112 μm, 388 pL and 125 μm, respectively. A single nozzle driven by jetting parameters optimized for stable satellite-free drop formation at 30 °C was used to deposit droplets into a row of 40 via holes within one printing swath. The printing resolution in the process direction was set to the pitch of the via holes and the cross process resolution was set to 1 μm (25400 dpi). The number of droplets deposited into a single via hole in one “set”, i.e. the number of printing swaths in the process direction having a minimal cross-process directional inter-swath 195 Digital Fabrication and Digital Printing: NIP31 Technical Program and Proceedings shift of 1 μm, was then set by the width of the bitmap pattern in the print recipe. The deposition delay between subsequent droplets in a single via hole within a set was controlled by the printing speed in the process direction. The delay and substrate temperature during printing and between sets was controlled. Three different strategies (A, B, C) based on these process parameter combinations were tested (Table 1). Table 1: TSV filling strategies and process parameters.